View SSD0859_1253093.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

solomon systech semiconductor technical data this document contains information on a new product. specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD0859 rev 1.0 p1/42 dec 2003 copyright ? 2003 solomon systech limited advance information 128 x 80 stn lcd segment / common 4 g/s driver with controller SSD0859
solomon systech dec 2003 p 2/42 rev 1.0 SSD0859 table of contents 1. general description ......................................................................................................... ........ 5 2. features .................................................................................................................... ..................... 5 3. ordering information ........................................................................................................ ...... 5 4. block diagram ............................................................................................................... .............. 6 5. die pad arrangement (SSD0859z die pin assignment).................................................... 7 6. pin descriptions ............................................................................................................ ............ 11 7. functional block descriptions......................................................................................... 13 8. command table ............................................................................................................... ........... 18 9. extended command table ..................................................................................................... 2 1 10. command descriptions....................................................................................................... .. 24 11. maximum ratings ............................................................................................................ ......... 28 12. electrical characteristics.............................................................................................. 29 13. ac electrical characteristics........................................................................................ 31 14. application circuit ........................................................................................................ ........ 33 15. package information........................................................................................................ .... 41
SSD0859 rev 1.0 p 3/42 dec 2003 solomon systech table of tables table 1 - ordering information................................................................................................. ............ 5 table 2 - SSD0859 die pad coordinates .......................................................................................... ... 8 table 3 - command table........................................................................................................ ........... 18 table 4 - extended command table ............................................................................................... .. 21 table 5 - maximum ratings (voltage referenced to v ss )................................................................ 28 table 6 - dc characteristics (voltages referenced to vss, vdd=1.8 to 3.3v, ta=-40 to 85c; unless otherwise specified.).............................................................................................. 29 table 7 - ac characteristics (ta=-40 to 85c, voltages referenced to vss, vdd=vci=2.7v, unless otherwise specified.).............................................................................................. 31 table 8 - i 2 c-bus timing characteristics (t a = -40 to 85 c, v dd = 1.8 to 3.3v, v ss =0v) ................ 32
solomon systech dec 2003 p 4/42 rev 1.0 SSD0859 table of figures figure 1 - SSD0859 block diagram ............................................................................................... ...... 6 figure 2 - SSD0859 die pad floor plan.......................................................................................... ..... 7 figure 3 - graphic display data ram (gddram) address map for SSD0859 (with vertical scroll value 48h) ..................................................................................................................... ..... 14 figure 4 - oscillator circuitry ................................................................................................ ............ 15 figure 5 - lcd display example ?0? ............................................................................................. .... 17 figure 6 - lcd driving signal from SSD0859.................................................................................. 17 figure 7 - contrast control voltage range curve ........................................................................... 25 figure 8 - contrast control flow ............................................................................................... ........ 25 figure 9 - i 2 c data bus interface driving waveform ......................................................................... 32 figure 10 - application circuit ................................................................................................ ........... 33 figure 11 - i 2 c-bus data format.......................................................................................................... 38 figure 12 - definition of the start and stop condition ..................................................................... 39 figure 13 - definition of the acknowledgement condition.............................................................. 39 figure 14 - definition of the data transfer condition ....................................................................... 40
SSD0859 rev 1.0 p 5/42 dec 2003 solomon systech 1. general description SSD0859 is a single-chip cmos lcd driver with controller for liquid crystal dot-matrix graphic display system. SSD0859 consists of 210 high voltage driving output pins for driving 128 segments and 80 commons and 1 icon line. SSD0859 display data directly from its internal 128x81x2 bits graphic display data ram (gddram). data/commands are sent from general mcu through i 2 c interface. SSD0859 embeds a dc-dc converter, a lcd voltage regulator, an on-chip bias divider, integrated bias capacitors, integrated booster capacitors and an on-chip oscillator, which reduce the number of external components. with the special design on minimizing power consumption and die/package layout, SSD0859 is suitable for any portable battery-driven applications requiring long operation period and compact size. 2. features 128x80 + 1 icon line, 4 gray-levels graphic display programmable multiplex ratio [16mux - 81mux] single supply operation, 1.8 v - 3.3v low current sleep mode on-chip voltage generator / external power supply software selectable 3x / 4x / 5x / 6x on-chip dc-dc converter on-chip oscillator on-chip bias dividers programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio maximum +15.0v lcd driving output voltage i 2 c interface on-chip 128x81x2 graphic display data ram re-mapping of row and column drivers vertical scrolling display offset control maximum 1mhz i 2 c interface 64 level internal contrast control external contrast control selectable lcd driving voltage temperature coefficients (2 settings) available in gold bump die 3. ordering information ordering part number seg com package form reference remark SSD0859z 128 80 + 1 gold bump die figure 2 on page 7 - table 1 - ordering information
solomon systech dec 2003 p 6/42 rev 1.0 SSD0859 4. block diagram figure 1 - SSD0859 block diagram /res sda sck sa0 com0 to com79 cxp vout vl5 vl4 vl3 vl2 vss gddram 128 x 81 x 2 bits lcd driving voltage generator 3x/4x/5x/ 6x dc/dc converter, voltage regulator, bias divider, contrast control, temperature compensation 209 bits latch icons seg0 ~seg127 hv buffer cell level shifter display timing generator oscillator level selector command decoder i 2 c interface command interface cl vss vdd vr intrs vci cxn vlref rvss cvss
SSD0859 rev 1.0 p 7/42 dec 2003 solomon systech 5. die pad arrangement (SSD0859z die pin assignment) figure 2 - SSD0859 die pad floor plan n ote: 1. the gold bumps face up in this diagram. 2. coordinates reference to center of the chip. 3. all dimensions and coordinates in um. 4. all alignment keys do not contain gold bump. 25 25 25 25 25 25 100 100 25 25 25 25 50 100 100 18 100 75 100 die size: 10915um x 1015um die thickness: 21mil bump height: typical 18m bump coplanarity <3m (within die) bump size: pad 1-129: 56 x 56um pad 130-140,335-345: 82 x 36um pad 142-333: 36 x 82um pad 141, 334: 56 x 82um n c com30 com29 com28 com27 com26 com25 com3 com2 com1 com0 icons seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 com40 com41 com42 com43 com66 com67 com68 com69 com70 com71 nc com72 com73 com79 icons n/c nc nc nc vr vout vout vout vout vout vout vout vout vout vout vout vout vout vout vout vl5 vl4 vl3 vl2 vss intrs vdd cxp cxn vss vss vss vss vss vss vss vss cvss cvss cvss cvss cvss cvss cvss cvss cvss cvss cvss cvss cvss rvss vlref vlref vlref vci vci vci vci vci vci vci vci vci vci vci vci vci vci vci vdd vdd vdd vdd vdd vdd vdd vdd nc nc sda sda sck sck test16 test15 test14 test13 test12 sa0 vdd test11 test10 test9 test8 vss test7 test6 test5 /res vdd test4 test3 vss test2 vdd vss test1 vdd en80 vss cl nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc pin #1 center: (-5050, 100) center: (5050, -200) 130 center: (5050, 100) center: (-5050, -200) y x (0,0) nc com31 com32 com38 com39 n/c 141 345 334 1 129
solomon systech dec 2003 p 8/42 rev 1.0 SSD0859 table 2 - SSD0859 die pad coordinates pad# signal x-pos y-pos pad# signal x-pos y-pos pad# signal x-pos y-pos 1 nc -4883.2 -353.5 45 test14 -1526.0 -353.5 89 cvss 1831.2 -353.5 2 nc -4806.9 -353.5 46 test15 -1449.7 -353.5 90 cvss 1907.5 -353.5 3 nc -4730.6 -353.5 47 test16 -1373.4 -353.5 91 cvss 1983.8 -353.5 4 nc -4654.3 -353.5 48 sck -1297.1 -353.5 92 cvss 2060.1 -353.5 5 nc -4578.0 -353.5 49 sck -1220.8 -353.5 93 cvss 2136.4 -353.5 6 nc -4501.7 -353.5 50 sda -1144.5 -353.5 94 vss 2212.7 -353.5 7 nc -4425.4 -353.5 51 sda -1068.2 -353.5 95 vss 2289.0 -353.5 8 nc -4349.1 -353.5 52 nc -991.9 -353.5 96 vss 2365.3 -353.5 9 nc -4272.8 -353.5 53 nc -915.6 -353.5 97 vss 2441.6 -353.5 10 nc -4196.5 -353.5 54 vdd -839.3 -353.5 98 vss 2517.9 -353.5 11 nc -4120.2 -353.5 55 vdd -763.0 -353.5 99 vss 2594.2 -353.5 12 nc -4043.9 -353.5 56 vdd -686.7 -353.5 100 vss 2670.5 -353.5 13 nc -3967.6 -353.5 57 vdd -610.4 -353.5 101 vss 2746.8 -353.5 14 nc -3891.3 -353.5 58 vdd -534.1 -353.5 102 cxn 2823.1 -353.5 15 nc -3815.0 -353.5 59 vdd -457.8 -353.5 103 cxp 2899.4 -353.5 16 nc -3738.7 -353.5 60 vdd -381.5 -353.5 104 vdd 2975.7 -353.5 17 nc -3662.4 -353.5 61 vdd -305.2 -353.5 105 intrs 3052.0 -353.5 18 nc -3586.1 -353.5 62 vci -228.9 -353.5 106 vss 3128.3 -353.5 19 nc -3509.8 -353.5 63 vci -152.6 -353.5 107 vl2 3204.6 -353.5 20 cl -3433.5 -353.5 64 vci -76.3 -353.5 108 vl3 3280.9 -353.5 21 vss -3357.2 -353.5 65 vci 0.0 -353.5 109 vl4 3357.2 -353.5 22 en80 -3280.9 -353.5 66 vci 76.3 -353.5 110 vl5 3433.5 -353.5 23 vdd -3204.6 -353.5 67 vci 152.6 -353.5 111 vout 3509.8 -353.5 24 test1 -3128.3 -353.5 68 vci 228.9 -353.5 112 vout 3586.1 -353.5 25 vss -3052.0 -353.5 69 vci 305.2 -353.5 113 vout 3662.4 -353.5 26 vdd -2975.7 -353.5 70 vci 381.5 -353.5 114 vout 3738.7 -353.5 27 test2 -2899.4 -353.5 71 vci 457.8 -353.5 115 vout 3815.0 -353.5 28 vss -2823.1 -353.5 72 vci 534.1 -353.5 116 vout 3891.3 -353.5 29 test3 -2746.8 -353.5 73 vci 610.4 -353.5 117 vout 3967.6 -353.5 30 test4 -2670.5 -353.5 74 vci 686.7 -353.5 118 vout 4043.9 -353.5 31 vdd -2594.2 -353.5 75 vci 763.0 -353.5 119 vout 4120.2 -353.5 32 /res -2517.9 -353.5 76 vci 839.3 -353.5 120 vout 4196.5 -353.5 33 test5 -2441.6 -353.5 77 vlref 915.6 -353.5 121 vout 4272.8 -353.5 34 test6 -2365.3 -353.5 78 vlref 991.9 -353.5 122 vout 4349.1 -353.5 35 test7 -2289.0 -353.5 79 vlref 1068.2 -353.5 123 vout 4425.4 -353.5 36 vss -2212.7 -353.5 80 rvss 1144.5 -353.5 124 vout 4501.7 -353.5 37 test8 -2136.4 -353.5 81 cvss 1220.8 -353.5 125 vout 4578.0 -353.5 38 test9 -2060.1 -353.5 82 cvss 1297.1 -353.5 126 vr 4654.3 -353.5 39 test10 -1983.8 -353.5 83 cvss 1373.4 -353.5 127 nc 4730.6 -353.5 40 test11 -1907.5 -353.5 84 cvss 1449.7 -353.5 128 nc 4806.9 -353.5 41 vdd -1831.2 -353.5 85 cvss 1526.0 -353.5 129 nc 4883.2 -353.5 42 sa0 -1754.9 -353.5 86 cvss 1602.3 -353.5 43 test12 -1678.6 -353.5 87 cvss 1678.6 -353.5 130 nc 5290.5 -364.3 44 test13 -1602.3 -353.5 88 cvss 1754.9 -353.5 131 com39 5290.5 -309.7
SSD0859 rev 1.0 p 9/42 dec 2003 solomon systech pad# signal x-pos y-pos pad# signal x-pos y-pos pad# signal x-pos y-pos 132 com38 5290.5 -255.1 176 seg2 3357.9 341.5 221 seg47 900.9 341.5 133 com37 5290.5 -200.5 177 seg3 3303.3 341.5 222 seg48 846.3 341.5 134 com36 5290.5 -145.9 178 seg4 3248.7 341.5 223 seg49 791.7 341.5 135 com35 5290.5 -91.3 179 seg5 3194.1 341.5 224 seg50 737.1 341.5 136 com34 5290.5 -36.7 180 seg6 3139.5 341.5 225 seg51 682.5 341.5 137 com33 5290.5 17.9 181 seg7 3084.9 341.5 226 seg52 627.9 341.5 138 com32 5290.5 72.5 182 seg8 3030.3 341.5 227 seg53 573.3 341.5 139 com31 5290.5 127.1 183 seg9 2975.7 341.5 228 seg54 518.7 341.5 140 nc 5290.5 181.7 184 seg10 2921.1 341.5 229 seg55 464.1 341.5 185 seg11 2866.5 341.5 230 seg56 409.5 341.5 141 nc 5275.9 341.5 186 seg12 2811.9 341.5 231 seg57 354.9 341.5 142 com30 5214.3 341.5 187 seg13 2757.3 341.5 232 seg58 300.3 341.5 143 com29 5159.7 341.5 188 seg14 2702.7 341.5 233 seg59 245.7 341.5 144 com28 5105.1 341.5 189 seg15 2648.1 341.5 234 seg60 191.1 341.5 145 com27 5050.5 341.5 190 seg16 2593.5 341.5 235 seg61 136.5 341.5 146 com26 4995.9 341.5 191 seg17 2538.9 341.5 236 seg62 81.9 341.5 147 com25 4941.3 341.5 192 seg18 2484.3 341.5 237 seg63 27.3 341.5 148 com24 4886.7 341.5 193 seg19 2429.7 341.5 238 seg64 -27.3 341.5 149 com23 4832.1 341.5 194 seg20 2375.1 341.5 239 seg65 -81.9 341.5 150 com22 4777.5 341.5 195 seg21 2320.5 341.5 240 seg66 -136.5 341.5 151 com21 4722.9 341.5 196 seg22 2265.9 341.5 241 seg67 -191.1 341.5 152 com20 4668.3 341.5 197 seg23 2211.3 341.5 242 seg68 -245.7 341.5 153 com19 4613.7 341.5 198 seg24 2156.7 341.5 243 seg69 -300.3 341.5 154 com18 4559.1 341.5 199 seg25 2102.1 341.5 244 seg70 -354.9 341.5 155 com17 4504.5 341.5 200 seg26 2047.5 341.5 245 seg71 -409.5 341.5 156 com16 4449.9 341.5 201 seg27 1992.9 341.5 246 seg72 -464.1 341.5 157 com15 4395.3 341.5 202 seg28 1938.3 341.5 247 seg73 -518.7 341.5 158 com14 4340.7 341.5 203 seg29 1883.7 341.5 248 seg74 -573.3 341.5 159 com13 4286.1 341.5 204 seg30 1829.1 341.5 249 seg75 -627.9 341.5 160 com12 4231.5 341.5 205 seg31 1774.5 341.5 250 seg76 -682.5 341.5 161 com11 4176.9 341.5 206 seg32 1719.9 341.5 251 seg77 -737.1 341.5 162 com10 4122.3 341.5 207 seg33 1665.3 341.5 252 seg78 -791.7 341.5 163 com9 4067.7 341.5 208 seg34 1610.7 341.5 253 seg79 -846.3 341.5 164 com8 4013.1 341.5 209 seg35 1556.1 341.5 254 seg80 -900.9 341.5 165 com7 3958.5 341.5 210 seg36 1501.5 341.5 255 seg81 -955.5 341.5 166 com6 3903.9 341.5 211 seg37 1446.9 341.5 256 seg82 -1010.1 341.5 167 com5 3849.3 341.5 212 seg38 1392.3 341.5 257 seg83 -1064.7 341.5 168 com4 3794.7 341.5 213 seg39 1337.7 341.5 258 seg84 -1119.3 341.5 169 com3 3740.1 341.5 214 seg40 1283.1 341.5 259 seg85 -1173.9 341.5 170 com2 3685.5 341.5 215 seg41 1228.5 341.5 260 seg86 -1228.5 341.5 171 com1 3630.9 341.5 216 seg42 1173.9 341.5 261 seg87 -1283.1 341.5 172 com0 3576.3 341.5 217 seg43 1119.3 341.5 262 seg88 -1337.7 341.5 173 icons 3521.7 341.5 218 seg44 1064.7 341.5 263 seg89 -1392.3 341.5 174 seg0 3467.1 341.5 219 seg45 1010.1 341.5 264 seg90 -1446.9 341.5 175 seg1 3412.5 341.5 220 seg46 955.5 341.5 265 seg91 -1501.5 341.5
solomon systech dec 2003 p 10/42 rev 1.0 SSD0859 pad# signal x-pos y-pos pad# signal x-pos y-pos 266 seg92 -1556.1 341.5 311 com49 -4013.1 341.5 267 seg93 -1610.7 341.5 312 com50 -4067.7 341.5 268 seg94 -1665.3 341.5 313 com51 -4122.3 341.5 269 seg95 -1719.9 341.5 314 com52 -4176.9 341.5 270 seg96 -1774.5 341.5 315 com53 -4231.5 341.5 271 seg97 -1829.1 341.5 316 com54 -4286.1 341.5 272 seg98 -1883.7 341.5 317 com55 -4340.7 341.5 273 seg99 -1938.3 341.5 318 com56 -4395.3 341.5 274 seg100 -1992.9 341.5 319 com57 -4449.9 341.5 275 seg101 -2047.5 341.5 320 com58 -4504.5 341.5 276 seg102 -2102.1 341.5 321 com59 -4559.1 341.5 277 seg103 -2156.7 341.5 322 com60 -4613.7 341.5 278 seg104 -2211.3 341.5 323 com61 -4668.3 341.5 279 seg105 -2265.9 341.5 324 com62 -4722.9 341.5 280 seg106 -2320.5 341.5 325 com63 -4777.5 341.5 281 seg107 -2375.1 341.5 326 com64 -4832.1 341.5 282 seg108 -2429.7 341.5 327 com65 -4886.7 341.5 283 seg109 -2484.3 341.5 328 com66 -4941.3 341.5 284 seg110 -2538.9 341.5 329 com67 -4995.9 341.5 285 seg111 -2593.5 341.5 330 com68 -5050.5 341.5 286 seg112 -2648.1 341.5 331 com69 -5105.1 341.5 287 seg113 -2702.7 341.5 332 com70 -5159.7 341.5 288 seg114 -2757.3 341.5 333 com71 -5214.3 341.5 289 seg115 -2811.9 341.5 334 nc -5275.9 341.5 290 seg116 -2866.5 341.5 291 seg117 -2921.1 341.5 335 nc -5290.5 181.7 292 seg118 -2975.7 341.5 336 com72 -5290.5 127.1 293 seg119 -3030.3 341.5 337 com73 -5290.5 72.5 294 seg120 -3084.9 341.5 338 com74 -5290.5 17.9 295 seg121 -3139.5 341.5 339 com75 -5290.5 -36.7 296 seg122 -3194.1 341.5 340 com76 -5290.5 -91.3 297 seg123 -3248.7 341.5 341 com77 -5290.5 -145.9 298 seg124 -3303.3 341.5 342 com78 -5290.5 -200.5 299 seg125 -3357.9 341.5 343 com79 -5290.5 -255.1 300 seg126 -3412.5 341.5 344 icons -5290.5 -309.7 301 seg127 -3467.1 341.5 345 nc -5290.5 -364.3 302 com40 -3521.7 341.5 303 com41 -3576.3 341.5 304 com42 -3630.9 341.5 305 com43 -3685.5 341.5 306 com44 -3740.1 341.5 307 com45 -3794.7 341.5 308 com46 -3849.3 341.5 309 com47 -3903.9 341.5 310 com48 -3958.5 341.5
SSD0859 rev 1.0 p 11/42 dec 2003 solomon systech 6. pin descriptions res this pin is reset signal input. when the pin is low, initialization of the chip is executed. sda, sck & sa0 these pins are bi-directional data bus to be connected to the mcu in i 2 c-bus interface. please refer to the section: iic communication interface on page 13 for detail pin descriptions. intrs this pin is an input pin to enable the internal resistor network for the voltage regulator when intrs is high. when external regulator is used, this pin must be connected to vss, and external resistor r1/r2 should be connected to vout, vr and vss. vdd this pin is power supply. vss this is a logic ground pin. it must connect to gnd from external supply. rvss this pin is the ground for internal voltage regulator. it must connect to same external gnd of cvss. cvss this is an analog ground pin. it must connect to gnd from external supply. vlref this pin is the reference voltage for internal operational amplifiers. it must connect to vdd / vss depends on the panel loading. connect to vss for small panel, while connect to vdd for large panel. vci reference voltage input for internal dc-dc converter. the voltage of generated vout equals to the multiple factor (3x, 4x, 5x or 6x) times vci with respect to vss. note: voltage at this input pin must be larger than or equal to vdd. cxp, cxn connect an external capacitor to these pins when 6x dc-dc converter factor is set. vout this pin is the most positive lcd driving voltage. it can be supplied externally or generated by the internal regulator. vr this pin is an input of the internal voltage regulator. when the internal resistors network for the voltage regulator is disabled (intrs is pulled low), external resistors should be connected between vss and vr, and vr and vout, respectively (please refer to application circuit). vl5, vl4, vl3 and vl2 these are lcd driving voltages. these pins should not be connected to any signal pins nor shorted together. they should be left open. they have the following relationship: vout > vl5 > vl4 > vl3 > vl2 > vss
solomon systech dec 2003 p 12/42 rev 1.0 SSD0859 1:a bias vl5 (a-1)/a*vout vl4 (a-2)/a*vout vl3 2/a*vout vl2 1/a*vout com0 - com79 these pins provide the row driving signal com0 - com79 to the lcd panel. icons this pin is the special icon line com signal output. seg0 - seg127 these pins provide the lcd column driving signal. their voltage level is vss during sleep mode and standby mode. cl this pin is the external clock input for the device if external clock mode is selected by software command. under por operation, this pin should be left opened and internal oscillator will be used after power on reset. en80 this pin must be connected to vdd. test1, test3-test11 these pins should be connected to vss. test2, test12-test16 these pins can be either connected to vss or vdd. nc these no connection pins should not be connected to any signal pins nor shorted together. they should be left open.
SSD0859 rev 1.0 p 13/42 dec 2003 solomon systech 7. functional block descriptions command decoder input is directed to the command decoder based on the input of control byte, which consists of a d/c bit and a r/w bit. for further information about the control byte, please refer to the section ?i 2 c-bus write data and read register status? on page 38. if both the d/c bit and the r/w bit are low, the input signal is interpreted as a command. it will be decoded and written to the corresponding command register. if the d/c bit is high and the r/w bit is low, input signal is written to graphic display data ram (gddram). i 2 c communication interface the iic communication interface consists of slave address bit (sa0), i 2 c-bus data signal (sda) and i 2 c-bus clock signal (sck). both the sda and the sck must be connected to pull-up resistors. there is also an input signal res , which is used for the initialization of device. a) slave address bit (sa0) SSD0859 has to recognize the slave address before transmitting or receiving any information by the i 2 c-bus. the device will respond to the slave address following by the slave address bit (?sa0? bit) and the read/write select bit (?r/w? bit) with the following byte format, b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 1 1 1 0 sa0 r/w ?sa0? bit provides an extension bit for the slave address. either ?0111100? or ?0111101? can be selected as the slave address of SSD0859. ?r/w? bit determines the i 2 c-bus interface is operating at either write mode or read status mode. b) i 2 c-bus data signal (sda) sda acts as a communication channel between the transmitter and the receiver. the data and the acknowledgement are sent through the sda. it should be noticed that the ito track resistance and the pulled-up resistance at ?sda? pin becomes a voltage potential divider. as a result, the acknowledgement would not be possible to attain a valid logic 0 level in ?sda?. c) i 2 c-bus clock signal (sck) the transmission of information in the i 2 c-bus is following a clock signal, sck. each transmission of data bit is taken place during a single clock period of sck. graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 128 x 81 x 2 = 20736bits. figure 3 is a description of the gddram address map. for mechanical flexibility, remapping on both segment and common outputs are provided respectively. for vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the ram data to be mapped to the display. figure 3 shows the cases in which the display start line register are set at 48h.
solomon systech dec 2003 p 14/42 rev 1.0 SSD0859 page address d3 d2 d1 d0 line address com output (display startline = 0) com output (display startline = 48h) d0(lsb) ---------- 00 com0 com8 d1 ---------- 01 com1 com9 d2 ---------- 02 com2 com10 d3 ---------- 03 com3 com11 d4 ---------- 04 com4 com12 d5 ---------- 05 com5 com13 d6 ---------- 06 com6 com14 0 0 0 0 d7(msb) ---------- 07 com7 com15 d0(lsb) ---------- 08 com8 com16 d1 ---------- 09 com9 com17 d2 ---------- 0a com10 com18 d3 ---------- 0b com11 com19 d4 ---------- 0c com12 com20 d5 ---------- 0d com13 com21 d6 ---------- 0e com14 com22 0 0 0 1 d7(msb) ---------- 0f com15 com23 ---------- ---------- ---------- ---------- ---------- ---------- ---------- | | | | ---------- d0(lsb) ---------- 40 com64 com72 d1 ---------- 41 com65 com73 d2 ---------- 42 com66 com74 d3 ---------- 43 com67 com75 d4 ---------- 44 com68 com76 d5 ---------- 45 com69 com77 d6 ---------- 46 com70 com78 1 0 0 0 d7(msb) ---------- 47 com71 com79 d0(lsb) ---------- 48 com72 com0 d1 ---------- 49 com73 com1 d2 ---------- 4a com74 com2 d3 ---------- 4b com75 com3 d4 ---------- 4c com76 com4 d5 ---------- 4d com77 com5 d6 ---------- 4e com78 com6 1 0 0 1 d7(msb) ---------- 4f com79 com7 1 0 1 0 d0 ---------- icons icons icons internal column address 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff adc = 0 00 01 02 03 7c 7d 7e 7f adc = 1 7f 7e 7d 7c 03 02 01 00 seg outputs seg0 seg1 seg2 seg3 seg124 seg125 seg126 seg127 figure 3 - graphic display data ram (gddram) address map for SSD0859 (with vertical scroll value 48h) mapping depends on com scan direction setting first byte second byte
SSD0859 rev 1.0 p 15/42 dec 2003 solomon systech oscillator circuit this module is an on-chip low power rc oscillator circuitry (figure 4). the oscillator generates the clock for the dc-dc voltage converter. this clock is also used in the display timing generator. enable oscillation circuit enable buffer internal resistor osc2 osc1 oscillator enable (cl) figure 4 - oscillator circuitry lcd driving voltage generator and regulator this module generates the lcd voltage needed for display output. it takes a single supply input and generates necessary bias voltages. it consists of: it consists of: 1. 3x, 4x, 5x and 6x dc-dc voltage converter 2. bias divider if the output op-amp buffer option in set power control register command is enabled, this circuit block will divide the regulator output (v out ) to give the lcd driving levels (v l2 - v l5 ). the divider does not require external capacitors to reduce the external hardware and pin counts. 3. contrast control software control of 64 voltage levels of lcd voltage. 4. bias ratio selection circuitry software control of 1/4 to 1/10 bias ratio to match the characteristic of lcd panel. 5. self adjust temperature compensation circuitry provide 2 compensation grade selections to satisfy the various liquid crystal temperature grades. the grading can be selected by software control. defaulted temperature coefficient (tc) value is - 0.05%/c. 209 bit latch a register carries the display signal information. in 128x81 display mode, data will be fed to the hv- buffer cell and level-shifted to the required level. level selector level selector is a control of the display synchronization. display voltage can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell, which in turn outputs the com or seg lcd waveform. hv buffer cell (level shifter) hv buffer cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. the output is shifted out with an internal frm clock, which comes from the display timing generator. the voltage levels are given by the level selector, which is synchronized with the internal m signal. internal resisto r
solomon systech dec 2003 p 16/42 rev 1.0 SSD0859 reset circuit when res input is low, the chip is initialized to the following: 1. page address is set to 0 2. column address is set to 0 3. display is off 4. display start line is set to 0 (gddram page 0, d0) 5. display offset is set to 0 (com0 is mapped to row0) 6. 128x80 display mode 7. normal/reverse display is normal 8. n-line inversion register is 0 9. entire display is off 10. power control register (vc, vr, vf) is set to (0,0,0) 11. 3x booster is selected 12. internal resistor ratio register is set to 0h 13. software contrast is set to 32 14. lcd bias ratio is set to 1/10 15. normal scan direction of com outputs 16. segment remap is disabled (seg0 display column address 0) 17. internal oscillator is off 18. test mode is off 19. temperature coefficient is set to ptc0 (-0.05%) 20. icon display line is off when reset command is issued, the following parameters are initialized only: 1. page address is set to 0 2. column address is set to 0 3. initial display line is set to 0 (point to display ram page 0, d0) 4. internal resistor ratio register is set to 0h 5. software contrast is set to 32
SSD0859 rev 1.0 p 17/42 dec 2003 solomon systech lcd panel driving waveform the following is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms shown in figure 5 and 6 illustrate the desired multiplex scheme with n-line inversion feature is disabled (default). figure 5 - lcd display example ?0? figure 6 - lcd driving signal from SSD0859 time slot com0 com1 seg0 seg1 m v l6 v l5 v l4 v l3 v l2 v ss v l6 v l5 v l4 v l3 v l2 v ss v l6 v l5 v l4 v l3 v l2 v ss v l6 v l5 v l4 v l3 v l2 v ss * note: n is the number of multiplex ratio including icon line. if it is enabled, n is equal to 80 on por 1 2 3 4 5 6 7 8 9 . . . n * 1 2 3 4 5 6 7 8 9 . . . n * 1 2 3 4 5 6 7 8 9 . . n * 1 2 3 4 5 6 7 8 9 . . . n * com1 com2 com3 com4 com5 com6 com7 e g 1 e g 2 e g 3 e g 4 com0 e g 0
solomon systech dec 2003 p 18/42 rev 1.0 SSD0859 8. command table table 3 - command table hex d7 d6 d5 d4 d3 d2 d1 d0 command description 00~0f 0 0 0 0 c3 c2 c1 c0 set lower column address set the lower nibble of the column address pointer for ram access. the pointer is reset to 0 after rest. 10~17 0 0 0 1 0 c6 c5 c4 set upper column address set the upper nibble of the column address pointer for ram access. the pointer is reset to 0 after rest. 18~1f reserved reserved 20~27 0 0 1 0 0 r2 r1 r0 set internal regulator resistor ratio the internal regulator gain (1+r2/r1)vout increases as r2r1r0 is increased from 000b to 111b. the factor, 1+r2/r1, is given by: r2r1r0 = 000: 2.84 (por) r2r1r0 = 001: 3.71 r2r1r0 = 010: 4.57 r2r1r0 = 011: 5.44 r2r1r0 = 100: 6.30 r2r1r0 = 101: 7.16 r2r1r0 = 110: 8.03 r2r1r0 = 111: 8.89 28~2f 0 0 1 0 1 vc vr vf set power control register vc=0: turns off the internal voltage booster (por) vc=1: turns on the internal voltage booster vr=0: turns off the internal regulator (por) vr=1: turns on the internal regulator vf=0: turns off the output op-amp buffer (por) vf=1: turns on the output op-amp buffer 30~3f reserved reserved 40~43 0 x 1 l6 0 l5 0 l4 0 l3 0 l2 x l1 x l0 set display start line the second command specifies the row address pointer (0-79) of the ram data to be displayed in com0. this command has no effect on icons. the pointer is set to 0 after reset. 44~47 0 x 1 c6 0 c5 0 c4 0 c3 1 c2 x c1 x c0 set display offset the second command specifies the mapping of first display line (com0) to one of row0~79. this command has no effect on icons. com0 is mapped to row0 after reset. 48~4b 0 x 1 d6 0 d5 0 d4 1 d3 0 d2 x d1 x d0 set multiplex ratio the second command specifies the number of lines, excluding icons, to be displayed. with icon is disabled (por), duties 1/16~1/80 could be selected. with icon enabled, the available duty ratios are 1/17~ 1/81.
SSD0859 rev 1.0 p 19/42 dec 2003 solomon systech hex d7 d6 d5 d4 d3 d2 d1 d0 command description 4c~4f 0 x 1 x 0 x 0 n4 1 n3 1 n2 x n1 x n0 set n-line inversion the second command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. register values from 00001b to 11111b are mapped to 3 lines to 33 lines respectively. value 00000b disables the n-line inversion, which is the por value. to avoid a fix polarity at some lines, it should be noted that the total number of mux (including the icon line) should not be a multiple of the lines of inversion (n). 50~56 0 1 0 1 0 b2 b1 b0 set lcd bias sets the lcd bias from 1/4 ~ 1/10 according to b2b1b0: 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7bias 100: 1/8 bias 101: 1/9 bias 110: 1/10 bias (por) 57~63 reserved reserved 64~67 0 1 1 0 0 1 b1 b0 set dc-dc converter factor sets the dc-dc multiplying factor from 3x to 6x b1b0: 00: 3x (por) 01: 4x 10: 5x 11: 6x 68~80 reserved reserved 81 1 x 0 x 0 c5 0 c4 0 c3 0 c2 0 c1 1 c0 set contrast control register the second command sets one of the 64 contrast levels. the darkness increase as the contrast level increase. the level is set to 32 after por. 82 1 1 0 1 0 1 0 1 0 x3 0 x2 1 x1 0 x0 otp setting set the desired vout voltage value: 0000: original contrast 0001: original contrast +1 step 0010: original contrast +2 steps 0011: original contrast +3 steps 0100: original contrast +4 steps 0101: original contrast +5 steps 0110: original contrast +6 steps 0111: original contrast +7 steps 1000: original contrast -8 steps 1001: original contrast -7 steps 1010: original contrast -6 steps 1011: original contrast -5 steps 1100: original contrast -4 steps 1101: original contrast -3 steps 1110: original contrast -2 steps 1111: original contrast -1 step 83 1 0 0 0 0 0 1 1 otp programming please refer the sequence of otp programming 84~87 reserved reserved
solomon systech dec 2003 p 20/42 rev 1.0 SSD0859 hex d7 d6 d5 d4 d3 d2 d1 d0 command description 88 1 wb3 0 wb2 0 wb1 0 wb0 1 wa3 0 wa2 0 wa1 0 wa0 set white mode, frame 2 nd & 1 st 89 1 wd3 0 wd2 0 wd1 0 wd0 1 wc3 0 wc2 0 wc1 1 wc0 set white mode, frame 4 th & 3 rd 8a 1 lb3 0 lb2 0 lb1 0 lb0 1 la3 0 la2 1 la1 0 la0 set light gray mode, frame 2 nd & 1 st 8b 1 ld3 0 ld2 0 ld1 0 ld0 1 lc3 0 lc2 1 lc1 1 lc0 set light gray mode, frame 4 th & 3 rd 8c 1 db3 0 db2 0 db1 0 db0 1 da3 1 da2 0 da1 0 da0 set dark gray mode, frame 2 nd & 1 st 8d 1 dd3 0 dd2 0 dd1 0 dd0 1 dc3 1 dc2 0 dc1 1 dc0 set dark gray mode, frame 4 th & 3 rd 8e 1 bb3 0 bb2 0 bb1 0 bb0 1 ba3 1 ba2 1 ba1 0 ba0 set black mode, frame 2 nd & 1 st 8f 1 bd3 0 bd2 0 bd1 0 bd0 1 bc3 1 bc2 1 bc1 1 bc0 set black mode, frame 4 th & 3 rd set gray scale mode and register. these are two-byte commands used to specify the contrast levels for the gray scale, 4 levels available. after power on reset, wa0~3 = wb0~3 = wc0~3 = wd0~3 = 0000 la0~3 = lb0~3 = lc0~3 = ld0~3 = 0000 da0~3 = db0~3 = dc0~3 = dd0~3 = 1111 ba0~3 = bb0~3 = bc0~3 = bd0~3 = 1111 memory content 1 st byte 2 nd byte gray mode 0 0 1 1 0 1 0 1 white light gray dark gray black 90~97 1 0 0 1 0 fr c pw m1 pw m0 set pwm and frc sets pwm and frc for gray-scale operation. frc = 0 : 4-frame (por) frc = 1 : 3-frame pwm1 pwm0 = 00 & 01 : 9-levels (por) pwm1 pwm0 = 10 : 12-levels pwm1 pwm0 = 11 : 15-levels 98~9f reserved reserved a0~a1 1 0 1 0 0 0 0 s0 set segment re- map s0=0: column address 00h is mapped to seg0 (por) s0=1: column address 7fh is mapped to seg0 a2~a3 1 0 1 0 0 0 1 c0 set icon enable c0=0: disable icon row (mux = 16 to 80, por) c0=1: enable icon row (mux = 17 to 81) a4~a5 1 0 1 0 0 1 0 e0 set entire display on/off e0=0: normal display (display according to ram contents, por) e0=1: all pixels are on regardless of the ram contents *note: this command will override the effect of ?set normal/inverse display? a6~a7 1 0 1 0 0 1 1 r0 set normal/inverse display r0=0: normal display (display according to ram contents, por) r0=1: inverse display (on and off pixels are inverted) *note: this command will not affect the display of the icon line a8~a9 1 0 1 0 1 0 0 s0 set power save mode s0=0: standby mode (por) s0=1: sleep mode
SSD0859 rev 1.0 p 21/42 dec 2003 solomon systech hex d7 d6 d5 d4 d3 d2 d1 d0 command description aa reserved reserved ab 1 0 1 0 1 0 1 1 start internal oscillator this command starts the internal oscillator. note that the oscillator is off after reset, so this instruction must be executed for initialization. ac~ad reserved reserved ae~af 1 0 1 0 1 1 1 d0 set display on/off d0=0: display off (por) d0=1: display on b0~bf 1 0 1 1 p3 p2 p1 p0 set page address set gddram page address (0~10) using p3p2p1p0 for ram access. the page address is sets to 0 after reset. c0~cf 1 1 0 0 s0 x x x set com output scan direction s0=0: normal mode (por) s0=1: remapped mode. com0 to com[n-1] becomes com[n-1] to com0 when the duty is set to n. see figure 3 as an example for n equals to 80. *note: this command will not affect the display of the icon lines d0~e0 reserved reserved e1 1 1 1 0 0 0 0 1 exit power-save mode dc-dc converter, regulator and divider status before entering the power-save mode is restored. at por, power-save mode is released. e2 1 1 1 0 0 0 1 0 software reset initialize some internal registers e3 reserved reserved e4 1 1 1 0 0 1 0 0 exit n-line inversion the frame will be inverted once per frame e5~e7 reserved reserved e9~ef reserved reserved f0~ff 1 1 1 1 x x x x extended features test mode commands and extended features, see extended command table. 9. extended command table table 4 - extended command table bit pattern command description 11110001 00001 x 2 x 1 x 0 x 2 x 1 x 0 : set tc value x 2 x 1 x 0 = 000: -0.05%/ c (por) x 2 x 1 x 0 = 001: -0.07%/ c 11110111 0000000 x 0 select oscillator source x 0 = 0: internal rc oscillator is selected (por) x 0 = 1: external oscillator from cl pin is selected 11110010 00000 x 2 x 1 x 0 oscillator adjustment x 2 x 1 x 0 = 000: -14.5% x 2 x 1 x 0 = 001: -10% x 2 x 1 x 0 = 011: 0 (por) x 2 x 1 x 0 = 000: +7.5% x 2 x 1 x 0 = 000: +15.5% x 2 x 1 x 0 = 000: +26% x 2 x 1 x 0 = 000: +36%
solomon systech dec 2003 p 22/42 rev 1.0 SSD0859 bit pattern command description 11111101 xxxx0 x 2 10 lock / unlock interface x 2 = 0 : unlock the ic. the driver accepts any command and data written. x 2 = 1 : lock the ic. the driver ignores all command and data written, except the unlock command or pin reset. 11110110 000 x 4 x 3 x 2 x 1 x 0 frame frequency adjust (please find the default setting in the following table) framefq x 2 x 1 x 0 = 000: 0 x 2 x 1 x 0 = 001: 1 x 2 x 1 x 0 = 010: 2 x 2 x 1 x 0 = 011: 3 x 2 x 1 x 0 = 100: 4 x 2 x 1 x 0 = 101: 5 x 2 x 1 x 0 = 110: 6 x 2 x 1 x 0 = 111: 7 fosc x 4 x 3 = 00: 58khz x 4 x 3 = 01: 77khz x 4 x 3 = 10: 92khz x 4 x 3 = 11: 115khz 11110101 1000 x 3 010 low power mode x 3 = 1: disable low power mode (por) x 3 = 0: enable low power mode 11111100 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 crosstalk compensation upper bits adjustment x 7 x 6 x 5 x 4 = 0000: no adjustment (por) x 7 x 6 x 5 x 4 = 0001: + 1 step x 7 x 6 x 5 x 4 = 0010: + 2 steps x 7 x 6 x 5 x 4 = 0011: + 3 steps x 7 x 6 x 5 x 4 = 0100: + 4 steps x 7 x 6 x 5 x 4 = 0101: + 5 steps x 7 x 6 x 5 x 4 = 0110: + 6 steps x 7 x 6 x 5 x 4 = 0111: + 7 steps x 7 x 6 x 5 x 4 = 1000: - 7 steps x 7 x 6 x 5 x 4 = 1001: - 7 steps x 7 x 6 x 5 x 4 = 1010: - 6 steps x 7 x 6 x 5 x 4 = 1011: - 5 steps x 7 x 6 x 5 x 4 = 1100: - 4 steps x 7 x 6 x 5 x 4 = 1101: - 3 steps x 7 x 6 x 5 x 4 = 1110: - 2 steps x 7 x 6 x 5 x 4 = 1111: - 1 step lower bits adjustment x 3 x 2 x 1 x 0 = 0000: no adjustment (p0r) x 3 x 2 x 1 x 0 = 0001: + 1 step x 3 x 2 x 1 x 0 = 0010: + 2 steps x 3 x 2 x 1 x 0 = 0011: + 3 steps x 3 x 2 x 1 x 0 = 0100: + 4 steps x 3 x 2 x 1 x 0 = 0101: + 5 steps x 3 x 2 x 1 x 0 = 0110: + 6 steps x 3 x 2 x 1 x 0 = 0111: + 7 steps x 3 x 2 x 1 x 0 = 1000: - 7 steps x 3 x 2 x 1 x 0 = 1001: - 7 steps x 3 x 2 x 1 x 0 = 1010: - 6 steps x 3 x 2 x 1 x 0 = 1011: - 5 steps x 3 x 2 x 1 x 0 = 1100: - 4 steps x 3 x 2 x 1 x 0 = 1101: - 3 steps x 3 x 2 x 1 x 0 = 1110: - 2 steps x 3 x 2 x 1 x 0 = 1111: - 1 step the result for upper 4 bits & lower 4 bits are additive. other than the above set test mode reserved
SSD0859 rev 1.0 p 23/42 dec 2003 solomon systech frame frequency default setting frame frequency = fosc / [mux x (framefq + 1) x pwm] mux (icon enable) framefq pwm fosc mux<=17 2 5 4 15 12 9 58khz 92khz 58khz 18<=mux<=33 1 1 2 15 12 9 77khz 58khz 77khz 34<=mux<=49 0 1 1 15 12 9 58khz 92khz 77khz 50<=mux<=65 0 0 1 15 12 9 77khz 58khz 92khz 66<=mux<=81 0 0 0 15 12 9 92khz 77khz 58khz pwm is defined in command set pwm and frc. read status byte a 8 bits status byte will be placed onto the data bus when a read operation is performed if d/ c is low. the status byte is defined as following: d7 d6 d5 d4 d3 d2 d1 d0 comment busy on res 0 1 0 ds1 ds0 busy=0 : chip is idle busy=1 : chip is executing instruction on=0 : display is off on=1 : display is on res =0: chip is idle res =1: chip is executing reset ds1, ds0 = 01: SSD0859 * no need to resend the command again if it is set previously. the read / write action to the display data ram does not depend on the display mode. this means the user can change the ram content whether the target ram content is being displayed or not.
solomon systech dec 2003 p 24/42 rev 1.0 SSD0859 10. command descriptions set display on/off this command turns the display on/off, by the value of the lsb. set display start line this command is to set display start line register to determine starting address of display ram to be displayed by selecting a value from 0 to 79. with value equals to 0, d0 of page 0 is mapped to com0. with value equals to 1, d1 of page0 is mapped to com0. the display start line values of 0 to 9 are assigned to page 0 to 9. set page address this command positions the page address to 0 to 8/10 possible positions in gddram. refer to figure 3. set higher column address this command specifies the higher nibble of the 7-bit column address of the display data ram. the column address will be incremented by each data access after it is pre-set by the mcu and returning to 0 once overflow (>127). set lower column address this command specifies the lower nibble of the 7-bit column address of the display data ram. the column address will be incremented by each data access after it is pre-set by the mcu and returning to 0 once overflow (>127). set segment re-map this commands changes the mapping between the display data column address and segment driver. it allows flexibility in layout during lcd module assembly. refer to figure 3. set normal/inverse display this command sets the display to be either normal/inverse. in normal display, a ram data of 1 indicates an ?on? pixel. while in reverse display, a ram data of 0 indicates an ?on? pixel. the icon line is not affected by this command. set entire display on/off this command forces the entire display, including the icon row, to be ?on? regardless of the contents of the display data ram. this command has priority over normal/inverse display. to execute this command, set display on command must be sent in advance. set lcd bias this command is used to select a suitable bias ratio (1/4 to 1/10) required for driving the particular lcd panel in use. the por default is set to 1/10 bias. software reset this command causes some of the internal status of the chip to be initialized: 1. page address is set to 0 2. column address is set to 0 3. initial display line is set to 0 (point to display ram page 0, d0) 4. internal resistor ratio register is set to (0,0,0) 5. software contrast is set to 32 set com output scan direction this command sets the scan direction of the com output allowing layout flexibility in lcd module assembly. set power control register this command turns on/off the various power circuits associated with the chip.
SSD0859 rev 1.0 p 25/42 dec 2003 solomon systech set internal regulator resistors ratio this command is to enable any one of the eight internal resistor (irs) settings for different regulator gains when using internal regulator resistor network (intrs pin pulled high). the contrast control voltage range curves below is referred to the following formula: figure 7 - contrast control voltage range curve set contrast control register this command adjusts the contrast of the lcd panel by changing vout of the lcd drive voltage provided by the on-chip power circuits. vout is set with 64 steps (6-bit) contrast control register. it is a compound commands: figure 8 - contrast control flow yes changes complete? set contrast control register contrast level data n o con out v r r v * 1 1 2 ? ? ? ? ? ? ? ? + = ref con v v * 210 63 1 ? ? ? ? ? ? ? ? = where , v vref 7 . 1 = vout (v)
solomon systech dec 2003 p 26/42 rev 1.0 SSD0859 set display offset the second command specifies the mapping of display start line (com0 if display start line register equals to 0) to one of row0-79. this command has no effect on icons. com0 is mapped to row0 after reset. set multiplex ratio this command switches default 80 multiplex mode to any multiplex from 16 to 80, if icon is disabled (por). when icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 81. the chip pads row0-row79 will be switched to corresponding com signal output. set power save mode this command forces the chip to enter standby or sleep mode. lsb of the command will define which mode will be entered. exit power save mode this command releases the chip from either standby or sleep mode and return to normal operation. set n-line inversion number of line inversion is set by this command for reducing crosstalk. 3 to 33-line inversion operations could be selected. at por, this operation is disabled. it should be noted that the total number of mux (including the icon line) should not be a multiple of the inversion number (n). or else, some lines will not be changed their polarity during frame change. exit n-line inversion this command releases the chip from n-line inversion mode. the driving waveform will be inverted once per frame after issuing this command. set dc-dc converter factor internal dc-dc converter factor is set by this command. 3x to 6x multiplying factors could be selected using this command. hardware configuration is used for 6x setup. set icon enable this command enable/disable the icon display. start internal oscillator after por, the internal oscillator is off. it should be turned on by sending this command to the chip. set gray scale mode (white/light gray/dark gray/black) command 88(hex) to 8f(hex) are used to specify the four gray levels? pulse width at the four possible frames. the four gray levels are called white, light gray, dark gray and black. each level is defined by 4 registers for 4 consecutive frames. for example, wa is a 4-bit register to define the pulse width of the 1 st frame in white mode. wb is a register for 2 nd frame in white mode etc. each command specifies two registers. for 4 frc, memory content frame 1 st byte 2 nd byte gray mode 1 st 2 nd 3 rd 4 th 0 0 white wa wb wc wd 0 1 light gray la lb lc ld 1 0 dark gray da db dc dd 1 1 black ba bb bc bd
SSD0859 rev 1.0 p 27/42 dec 2003 solomon systech for 3 frc, memory content frame 1 st byte 2 nd byte gray mode 1 st 2 nd 3 rd 4 th (no use) 0 0 white wa wb wc wd (xx) 0 1 light gray la lb lc ld (xx) 1 0 dark gray da db dc dc (xx) 1 1 black ba bb bc bc (xx) set pwm and frc this command selects the number of frames in frame rate control, or the number of levels in the pulse width modulation. set test mode this command forces the driver chip into its test mode for internal testing of the chip. under normal operation, user should not use this command. extended commands these commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip. these features are on top of general ones. set temperature coefficient (tc) value this command is to set 1 out of 2 different temperature coefficients in order to match various liquid crystal temperature grades. select oscillator source this command enables the external clock input from cl pin. oscillator adjustment this command is used to adjust the oscillator frequency to desired frame frequency. lock/unlock interface after sending the lock command, the interface will be disabled until the unlock command is received. the lock command is suggested whenever the lcd driver will not be accessed for some period. this can minimize incorrect data or command written due to noisy interface. low power mode the current consumption will be reduced when enter the low power mode. however, crosstalk compensation may be required after entered the low power mode. crosstalk compensation by using these double commands, 0xfc, 0xnn, to adjust the upper 4 bits and/or lower 4 bits, it can compensate the crosstalk.
solomon systech dec 2003 p 28/42 rev 1.0 SSD0859 11. maximum ratings table 5 - maximum ratings (voltage referenced to v ss ) symbol parameter value unit v dd -0.3 to 4.0 v v out supply voltage vss-0.3 to vss+18.0 v v ci booster supply voltage vdd to 4.0 v v in input voltage vss-0.3 to vdd+0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -40 to +85 o c t stg storage temperature range -65 to +150 o c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that vin and vout be constrained to the range v ss < or = (vin or v out ) < or = v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected.
SSD0859 rev 1.0 p 29/42 dec 2003 solomon systech 12. electrical characteristics table 6 - dc characteristics (voltages referenced to v ss , v dd =1.8 to 3.3v, t a =-40 to 85c; unless otherwise specified.) symbol parameter test condition min typ (at 25c) max unit v dd v ci logic circuit supply voltage range voltage generator circuit supply voltage range (absolute value referenced to v ss ) 1.8 v dd 2.7 2.7 3.3 3.3 v v i ac i dp1 i dp2 i sb i sleep access mode supply current drain (v dd + v ci pins) display mode supply current drain (v dd + v ci pins) display mode supply current drain (v dd + v ci pins) standby mode supply current drain (v dd + v ci pins) sleep mode supply current drain (v dd + v ci pins) v dd = v ci = 2.7v, voltage generator on, 4x converter enabled, write accessing, tcyc = 3.3mhz, frame freq.= 80hz, display on. v dd = v ci = 2.7v, vout=9v, voltage generator off, divider enabled, read/write halt, frame freq.=80hz, display on, v dd = v ci = 2.7v, vout=9v, voltage generator on, 4x dc-dc converter enabled divider enabled, read/write halt, frame freq.=80hz, display on. v dd = v ci = 2.7v, lcd driving waveform off, oscillator on, read/write halt. (@ 25 o c) v dd = v ci = 2.7v, lcd driving waveform off, oscillator off, read/write halt. (@ 25 o c) - - 200 11 0.9 456 27 270 20 2 550 30 340 40 5 ? ? a a a v out v lcd lcd driving voltage generator output (vout pin) dc-dc converter efficiency lcd driving voltage input (vout pin) display on, voltage generator enabled, dc/dc converter enabled, frame freq.=80hz, divider enabled. i cc < 20ua, 3x booster i cc < 20ua, 4x booster i cc < 20ua, 5x booster i cc < 20ua, 6x booster voltage generator disabled. vdd - - - - 4.0 - 93 91 90 88 - 15.0 - - - - 15.0 v % % % % v v oh1 v ol1 vout vout output high voltage (d 0 -d 7 ) output low voltage (d 0 -d 7 ) lcd driving voltage source (vout pin) lcd driving voltage source (vout pin) iout = +500 ? iout = -500 ? regulator enabled (vout voltage depends on int/ext contrast control) regulator disable 0.8*v dd 0.0 v dd - - - - floating v dd 0.2*v dd vout - 0.5 - v v v v vout v l5 v l4 v l3 v l2 vout v l5 v l4 v l3 v l2 lcd display voltage output (vout, v l5 , v l4 , v l3 , v l2 pins) lcd display voltage input (vout, v l5 , v l4 , v l3 , v l2 pins) divider enabled, 1:a bias ratio, a=4~10. voltage reference to v ss , external voltage generator, divider disabled - - - - - v l5 v l4 v l3 v l2 v ss vout (a- 1)/a*vout (a- 2)/a*vout 2/a*vout 1/a*vout - - - - - - - - - - vout vout v l5 v l4 v l3 v v v v v v v v v v
solomon systech dec 2003 p 30/42 rev 1.0 SSD0859 symbol parameter test condition min typ max unit i oh i ol i oz output high current source(d 0 -d 7 ) output low current drain (d 0 -d 7 ) output tri-state current drain source (d 0 -d 7 ) vout=v dd -0.4v vout=0.4v 50 - -1 - - - - -50 1 a a a c in input capacitance (all logic pins) 5 7.5 pf ? vout variation of vout output (1.8v < v dd < 3.3v) regulator enabled, internal contrast control enabled, set contrast control register = 0 - 2 - % ptc0 ptc1 temperature coefficient compensation temperature coefficient [por] temperature coefficient voltage regulator enabled voltage regulator enabled -0.04 -0.06 -0.05 -0.07 -0.06 -0.08 % % *the formula for the temperature coefficient is: % 100 * 25 1 * 0 50 0 50 ) / (% 0 0 0 0 0 0 c at v c c c at v c at v c tc out out out ? ? =
SSD0859 rev 1.0 p 31/42 dec 2003 solomon systech 13. ac electrical characteristics table 7 - ac characteristics (t a =-40 to 85c, voltages referenced to v ss , v dd =v ci =2.7v, unless otherwise specified.) symbol parameter test condition min typ (at 25c) max unit f frm frame frequency fosc / [mux x (framefq+1) x pwm] display on, set 128 x 81 graphic display mode, icon line enabled, 15pwm, default frame frequency setting 70 80 100 hz
solomon systech dec 2003 p 32/42 rev 1.0 SSD0859 table 8 - i 2 c-bus timing characteristics (t a = -40 to 85 c, v dd = 1.8 to 3.3v, v ss =0v) symbol parameter min typ max unit f sck i 2 c-bus clock frequency, sck 0 - 1 mhz t clkl i 2 c-bus clock low period, sck 1.3 - - s t clkh i 2 c-bus clock high period, sck 0.6 - - s t dsw i 2 c-bus data setup time, sda 100 - - s t dhw i 2 c-bus data hold time, sda 0.3 - 0.9 s t r rise time between sda & sck 20+0.1c bus - 300 ns t f fall time between sda & sck 20+0.1c bus - 300 ns c bus capacitive loadings at each i 2 c-bus channel - - 400 pf t dh, start i 2 c-bus hold time, start condition 0.6 - - s t ds, stop i 2 c-bus setup time, stop condition 0.6 - - s figure 9 - i 2 c data bus interface driving waveform t dh, start t ds, stop t dsw t dhw t r t f t clkh t clkl t cycle sd a sck
SSD0859 rev 1.0 p 33/42 dec 2003 solomon systech 14. application circuit figure 10 - application circuit SSD0859 die 81 mux (die face ip) v r vout vl4 vl5 vl3 vl2 sd a sc k sa0 intrs /res regulator divider circuit com38 com39 com79 icons seg127???????????????????????????seg0 display panel size 128 x 80 + 1 icon line icons com0 : : : : com38 com39 com40 com41 : : : : com79 seg0 ????????????????.????. seg127 remapped com scan direction [command: c8 remapped com scan direction [command: c8 remapped com scan direction [command: c8] : : : : : com0 segment remapped [command: a1) remapped com scan direction [command: c8 : : : : com41 com40 v ss / v dd v ss sck sda /res
solomon systech dec 2003 p 34/42 rev 1.0 SSD0859 application circuit: regulator circuit and bias divider circuit internal regulator and bias divider [command: 2f] external regulator and internal bias divider [command: 2d] 6x dc-dc converter factor [command: 67] capacitor = 0.1uf ? 1uf capacitor = 2.2uf ? 4.7uf vout vl5 vl4 vl3 vl2 vss remarks: intrs = ?h? v r vout vl5 vl4 vl3 vl2 capacitor = 2.2uf ? 4.7uf vss remarks: intrs = ?l? cxp cxn
SSD0859 rev 1.0 p 35/42 dec 2003 solomon systech otp programming circuit and sequence otp (one time programming) is a method to adjust the vout. in order to eliminate the variations of lcd module in term of contrast level, otp can be used to achieve the best contrast of every lcd modules. otp setting and programming should include two major steps of (1) find the otp offset and (2) otp programming as following, step 1. find the otp offset (1) hardware reset (sending an active low reset pulse to res pin) (2) send original initialization routines (3) set and display any test patterns (4) adjust the contrast value (0x81, 0x00~0x3f) until there is the best visual contrast (5) otp setting steps = contrast value of the best visual contrast - contrast value of original initialization example 1: contrast value of original initialization = 0x20 contrast value of the best visual contrast = 0x24 otp setting steps = 0x24 - 0x20 = +4 otp setting commands should be (0x82, 0xf4) example 2: contrast value of original initialization = 0x20 contrast value of the best visual contrast = 0x1b otp setting steps = 0x1b - 0x20 = -5 otp setting commands should be (0x82, 0xfb) step 2. otp programming (6) hardware reset (sending an active low reset pulse to res pin) (7) enable oscillator (0xab) (8) connect an external vcc (see diagram below) (9) send otp setting commands that we find in step 1 (0x82, 0xf0~0xff) (10) send otp programming command (0x83) (11) wait at least 2 seconds (12) hardware reset verify the result by repeating step 1. (2) ? (3) r + SSD0859 vout res 16-18v n ote: r = 1k ~ 10k oh m c = 1u ~ 4.7u f otp programming circuit c (8) (1) & (6) & (12) gnd gnd
solomon systech dec 2003 p 36/42 rev 1.0 SSD0859 flow chart of otp program start otp setting step = a djusted contrast value ? original contrast value connect an external voltage (16-18v) on vout pins i) send original initialization routines ii) set and display any test patterns iii ) ins p ect the contrast i) hardware reset ii) enable oscillator end yes n o a djust the contrast level to the best visual level a ccept the contrast level on panel? (i) send otp setting commands (ii) send otp programming command (iii) wait > 2 sec (iv) hardware reset (i) hardware reset (ii) send original initialization routines (iii) set and display any test patterns step 1 step 2
SSD0859 rev 1.0 p 37/42 dec 2003 solomon systech otp example program find the otp offset: 1. hardware reset by sending an active low reset pulse to res pin 2. command(0xab) \\enable oscillator command(0x2f) \\ turn on the internal voltage booster, internal regulator and output op-amp buffer; select booster level 3. command(0x48) \\ set duty ratio command(0x40) \\ 64mux command(0x55) \\ set biasing ratio (1/9 bias) 4. command(0x81) \\ set target gain and contrast. command(0x2d) \\ contrast = 45 command(0x24) \\ gain = 5.1 5. \\ set target display contents command(0xb0) \\ set page address command(0x00) \\ set lower nibble column address command(0x10) \\ set higher nibble column address data(?) \\ write target content to gddram command(0xaf) \\ set display on 6. otp offset calculation? target otp offset value is +3 otp programming: 7. hardware reset by sending an active low reset pulse to res pin 8. command(0xab) \\ enable oscillator 9. connect an external vout (16v-18v) 10. command(0x82) \\ set otp offset value to +3 (0011) command(0xf3) \\ 0001 x 3 x 2 x 1 x 0 , where x 3 x 2 x 1 x 0 is the otp offset value 11. command(0x83) \\ send the otp programming command 12. wait at least 2 seconds for programming wait time 13. hardware reset by sending an active low reset pulse to res pin verify the result: 14. after otp programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel
solomon systech dec 2003 p 38/42 rev 1.0 SSD0859 i 2 c-bus write data and read register status the i 2 c-bus interface gives access to write data and command into the device. please refer to figure 11 for the write mode of i 2 c-bus in chronological order. figure 11 - i 2 c-bus data format write mode 1) the master device initiates the data communication by a start condition. the definition of the start condition is shown in figure 12. the start condition is established by pulling the sda from high to low while the sck stays high. 2) the slave address is following the start condition for recognition use. for the SSD0859, the slave address is either ?b0111100? or ?b0111101? by changing the sa0 to high or low. 3) the write mode is established by setting the r/w bit to logic ?0?. 4) an acknowledgement signal will be generated after receiving one byte of data, including the slave address and the r/w bit. please refer to the figure 13 for the graphical representation of the acknowledge signal. the acknowledge bit is defined as that the sda line is pulled down during the high period of the acknowledgement related clock pulse. 5) after the transmission of the slave address, either the control byte or the data byte may be sent across the sda. a control byte mainly consists of co and d/c bits following by six ?0? ?s. a. if the co bit is set as logic ?0?, the transmission of the following information will contain data bytes only. b. the d/c bit determines the next data byte is acted as a command or a data. if the d/c bit is set to logic ?0?, it defines the following data byte as a command. if the d/c bit is set to logic ?1?, it defines the following data byte as a data which will be stored at the gddram. the gddram column address pointer will be increased by one automatically after each data write. 6) acknowledge bit will be generated after receiving each control byte or data byte. 0 1 1 1 1 0 slave address m 0 words n 0 bytes msb ??????.lsb 1 byte write mode sa0 p r/w d/c co a ck a ck control b y te data b y te a ck co d/c control b y te a ck data b y te a ck s 0 1 1 1 1 0 SSD0859 slave address note: co ? continuation bit d/c ? data / command selection bit ack ? acknowledgement sa0 ? slave address bit r/w ? read / write selection bit s ? start condition / p ? stop condition control b y te co d/c a ck 0 0 0 0 0 0 sa0 r/w 0 1 1 1 1 0 slave address read mode 0 1 1 1 1 0 s sa0 a ck status bytes a ck p r/w
SSD0859 rev 1.0 p 39/42 dec 2003 solomon systech data output by receiver data output by transmitter sck from master s start condition clock pulse for acknowledgement 1 8 9 non-acknowled g e 2 acknowled g e s start condition sda sck p stop condition sda sck t dh , start t ds , stop 7) the write mode will be finished when a stop condition is applied. the stop condition is also defined in figure 12. the stop condition is established by pulling the ?sda in? from low to high while the ?sck? stays high. figure 12 - definition of the start and stop condition figure 13 - definition of the acknowledgement condition please be noted that the transmission of the data bit has some limitations. 1. the data bit, which is transmitted during each sck pulse, must be kept at a stable state within the ?high? period of the clock pulse. please refer to the figure 14 for graphical representations. except in start or stop conditions, the data line can be switched only when the sck is low. 2. both the data line (sda) and the clock line (sck) should be pulled up by external resistors.
solomon systech dec 2003 p 40/42 rev 1.0 SSD0859 figure 14 - definition of the data transfer condition read mode (read status register) 1) no read mode in SSD0859 device change of data is allowed data line is stable; data is valid sda sck
SSD0859 rev 1.0 p 41/42 dec 2003 solomon systech 15. package information die tray dimensions spec mm (mil) w1 50.70 0.2 (1996) w2 45.50 0.2 (1791) h 4.05 0.2 (160) px 14.14 0.1 (557) py 2.33 0.1 (92) x 11.07 + 0.1/-0 (436) y 1.17 + 0.1/-0 (46) z 0.68 +0.1/-0 (27) x1 4.00 0.10 (157) n 54
solomon systech dec 2003 p 42/42 rev 1.0 SSD0859 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as compo nents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the solomon systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon sys- tech products for any such unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offic es, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regarding the design or manufacture of the part. http://www.solomon-systech.com

▲Up To Search▲

Price & Availability of SSD0859

	To Download SSD0859 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .